Methodology for Circuit Optimization by KENDRA L . MARKLE

This thesis presents a methodology for optimization of static and domino logic. The optimization techniques that are discussed were developed to improve propagation delay, dissipated power and area for circuit examples while taking noise margin and other constraints into consideration. Where needed, a weighted combination of the these four concerns is used to provide realistic goals and solutions. A guideline for the trade-offs between these goals is also presented. Static and domino circuits are analyzed to reveal the interdependencies between these design goals. Optimization is considered at three levels of resolution. Circuits which have individual transistors, P/N ratios, and entire standard cell gates parameterized are analyzed. The techniques for improving circuit performance that are discussed include recursive optimization, fast-path gates, skewed gates, and minor topology changes such as switching the logically equivalent pins of a gate, and combining and expanding small logic stages. The advantage of each method is characterized in terms of final circuit performance achieved.